Datasheet

78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6
R01UH0028EJ0400 Rev.4.00 482
Sep 27, 2010
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
f
XCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255)
Table 14-4. Set Value of TPS63 to TPS60
Base Clock (fXCLK6) Selection
Note 1
TPS63 TPS62 TPS61 TPS60
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
0 0 1 0 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
0 0 1 1 fPRS/2
3
250 kHz 625 kHz 1.25 MHz
0 1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
0 1 0 1 fPRS/2
5
62.5 kHz 156.25 kHz 312.5 kHz
0 1 1 0 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
0 1 1 1 fPRS/2
7
15.625 kHz 39.06 kHz 78.13 kHz
1 0 0 0 fPRS/2
8
7.813 kHz 19.53 kHz 39.06 kHz
1 0 0 1 fPRS/2
9
3.906 kHz 9.77 kHz 19.53 kHz
1 0 1 0 fPRS/2
10
1.953 kHz 4.88 kHz 9.77 kHz
1 0 1 1 TM50 output
Note 2
Other than above Setting prohibited
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
f
PRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 =
0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion
operation (TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty
= 50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
f
XCLK6
2 × k