Datasheet

78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6
R01UH0028EJ0400 Rev.4.00 464
Sep 27, 2010
Figure 14-12. Format of Port Mode Register 1 (PM1)
Address: FF21H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10
PM1n P1n pin I/O mode selection (n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Remark The figure shown above presents the format of port mode register 1 (PM1) of the 78K0/KB2-L
and 78K0/KC2-L.
Figure 14-13. Format of Port Mode Register 6 (PM6)
Address: FF26H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM6 1 1 1 1 1 1 PM61 PM60
PM6n P6n pin I/O mode selection (n = 0, 1)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Remark The figure shown above presents the format of port mode register 6 (PM6) of the 78K0/KY2-L
and 78K0/KA2-L.
(9) Port output mode register 6 (POM6)
This register sets the output mode of P60 and P61 in 1-bit units.
In the 78K0/KY2-L and 78K0/KA2-L, clear POM60 to 0 when using the P60/TxD6/SCLA0 pin as the data output of
serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-14. Format of Port Output Mode Register 6 (POM6)
Address: FF2AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
POM6 0 0 0 0 0 0 POM61 POM60
POM6n P6n pin output mode selection (n = 0 and 1)
0 Normal output (CMOS output) mode
1 N-ch open drain output (VDD tolerance) mode
Remark The figure shown above presents the format of port output mode register 6 (POM6) of the
78K0/KY2-L and 78K0/KA2-L.