Datasheet

78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6
R01UH0028EJ0400 Rev.4.00 459
Sep 27, 2010
Figure 14-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF56H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60
Base clock (fXCLK6) selection
Note 1
TPS63 TPS62 TPS61 TPS60
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
0 0 1 0 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
0 0 1 1 fPRS/2
3
250 kHz 625 kHz 1.25 MHz
0 1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
0 1 0 1 fPRS/2
5
62.5 kHz 156.25 kHz 312.5 kHz
0 1 1 0 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
0 1 1 1 fPRS/2
7
15.625 kHz 39.06 kHz 78.13 kHz
1 0 0 0 fPRS/2
8
7.813 kHz 19.53 kHz 39.06 kHz
1 0 0 1 fPRS/2
9
3.906 kHz 9.77 kHz 19.53 kHz
1 0 1 0 fPRS/2
10
1.953 kHz 4.88 kHz 9.77 kHz
1 0 1 1 TM50 output
Notes 2, 3
Other than above Setting prohibited
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. Note the following points when selecting the TM50 output as the base clock.
• Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0)
Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation
(TMC501 = 1).
• PWM mode (TMC506 = 1)
Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty =
50%.
It is not necessary to enable (TOE50 = 1) TO50 output in any mode.
3. 78K0/KB2-L and 78K0/KC2-L only
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)
TMC501: Bit 1 of TMC50