Datasheet

78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6

R01UH0028EJ0400 Rev.4.00 455

Sep 27, 2010

Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)

Address: FF50H After reset: 01H R/W

Symbol <7> <6> <5> 4 3 2 1 0

ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6

POWER6 Enables/disables operation of internal operation clock

Note 1

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit

Note 2

1 Enables operation of the internal operation clock

TXE6 Enables/disables transmission

0 Disables transmission (synchronously resets the transmission circuit).

1 Enables transmission

RXE6 Enables/disables reception

0 Disables reception (synchronously resets the reception circuit).

1 Enables reception

Notes 1. The output of the T

XD6 pin is fixed to the high level (when TXDLV6 = 0) and the input from the RXD6 pin is

fixed to the high level when POWER6 = 0 during transmission.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial interface

control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.