Datasheet

78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS
R01UH0028EJ0400 Rev.4.00 439
Sep 27, 2010
Cautions 1. Set the pin set to analog I/O to the input mode by using port mode register 2 (PM2).
2. If data is written to ADPC0, a wait cycle is generated. Do not write data to ADPC0 when the
peripheral hardware clock is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.
Figure 13-5. Format of A/D Port Configuration Register 1 (ADPC1)
(78K0/KB2-L and 78K0/KC2-L)
Address: FF2FH After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC1 0 0 0 0 0 ADPCS10 ADPCS9 ADPCS8
ADPCSn Digital I/O or analog I/O selection (n = 8 to 10)
0 Analog I/O
1 Digital I/O
Cautions 1. Set the pin set to analog I/O to the input mode by using port mode register 1 (PM1).
2. If data is written to ADPC1, a wait cycle is generated. Do not write data to ADPC1 when the
peripheral hardware clock is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.
(3) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-6. Format of Analog Input Channel Specification Register (ADS)
ADS0ADS1ADS2ADS3
ADS0ADS1ADS2ADS3
00ADOAS0
Analog input
channel
Input source
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
ANI8
ANI9
ANI10
PGAOUT
P20/ANI0 pin
P21/ANI1 pin or operational
amplifier 0 output signal
P22/ANI2 pin
P23/ANI3 pin
P24/ANI4 pin
P25/ANI5 pin
P26/ANI6 pin
P27/ANI7 pin
P10/ANI8 pin
P11/ANI9 pin or operational
amplifier 1 output signal
P12/ANI10 pin
PGA output signal
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
ADOAS0
<0><1><2><3>45<6>7
ADS
Address: FF0EH After reset: 00H R/W
Symbol
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Setting prohibitedOther than above
Cautions 1. Be sure to clear bits 4, 5, and 7 to “0”.
2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 1, 2
(PM1, PM2).
<R>