Datasheet

78K0/Kx2-L CHAPTER 12 A/D CONVERTER
R01UH0028EJ0400 Rev.4.00 427
Sep 27, 2010
The setting methods are described below.
<1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the
A/D converter mode register 0 (ADM0).
<2> Set bit 0 (ADCE) of ADM0 to 1.
<3> Set the channel to be used to analog input by using the A/D port configuration registers 0, 1 (ADPC0,
ADPC1) and port mode registers 1, 2 (PM1, PM2).
<4> Set the PGA operation to set the PGA output or the single AMP operation to set the operational amplifier
output for analog input. (refer to CHAPTER 13 OPERATIONAL AMPLIFIERS).
<5> Select a channel to be used by using the analog input channel specification register (ADS).
<6> Set bit 7 (ADCS) of ADM0 to 1 to start A/D conversion.
<7> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH, ADCRL).
<Change the channel>
<9> Set bit 0 (ADMK) of the interrupt mask flag register 1L (MK1L) to 1
Note
.
<10> Change the channel by using ADS to start A/D conversion.
<11> Clear bit 0 (ADIF) of the interrupt request flag register 1L (IF1L) to 0.
<12> Clear ADMK to 0
Note
.
<13> When one A/D conversion has been completed, an interrupt request signal (INTAD) is generated.
<14> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH, ADCRL).
<Complete A/D conversion>
<15> Clear ADCS to 0.
<16> Clear ADCE to 0.
Note Execute this only if interrupt servicing is used for A/D conversion.
Cautions 1. Make sure the period of <2> to <6> is 1
μ
s or more.
2. If the timing of <2> is earlier than that of <4>, <2> may be performed any time.
3. <2> can be omitted. However, ignore data of the first conversion after <6> in this case.
4. The period from <7> to <13> differs from the conversion time set using bits 5 to 1 (FR2 to
FR0, LV1, LV0) of ADM0. The period from <10> to <13> is the conversion time set using FR2
to FR0, LV1, and LV0.