Datasheet

78K0/Kx2-L CHAPTER 12 A/D CONVERTER
R01UH0028EJ0400 Rev.4.00 413
Sep 27, 2010
Cautions 1. Be sure to clear bits 4, 5, and 7 to “0”.
2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 1, 2,
7 (PM1, PM2, PM7).
3. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set
ADS after single AMP operation setting when selecting the operational amplifier output signal as
analog input (refer to CHAPTER 13 OPERATIONAL AMPLIFIERS).
4. If data is written to ADS, a wait cycle is generated. Do not write data to ADS when the peripheral
hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT.
(6) A/D port configuration registers 0, 1
Note
(ADPC0, ADPC1
Note
)
ADPC0 switches the P20/AMP0-/ANI0 to P27/ANI7 pins to digital I/O or analog I/O of port. Each bit of ADPC0
corresponds to a pin of port 2 and can be specified in 1-bit units.
ADPC1 switches the P10/AMP1-/ANI8 to P12/AMP1+/ANI10 or P70/ANI8 to P72/ANI10 pins to digital I/O or analog
I/O of port. Each bit of ADPC1 corresponds to a pin of P10 to P12 in port 1 or P70 to P72 in port7 and can be
specified in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears ADPC0 to 00H, sets ADPC1 of 78K0/KA2-L (32-pin products) to 00H, and sets ADPC1
of 78K0/KB2-L and 78K0/KC2-L to 07H.
Note 78K0/KA2-L (32-pin products), 78K0/KB2-L, and 78K0/KC2-L only
Figure 12-9. Format of A/D Port Configuration Registers 0, 1 (ADPC0, ADPC1) (1/3)
(a) 78K0/KY2-L
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 0 0 0 0 ADPCS3 ADPCS2 ADPCS1 ADPCS0
(b) 78K0/KA2-L (20-pin products)
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 0 0 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
(c) 78K0/KA2-L (25-pin products)
Address: FF2EH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC0 0 ADPCS6 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
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