Datasheet

78K0/Kx2-L CHAPTER 12 A/D CONVERTER
R01UH0028EJ0400 Rev.4.00 410
Sep 27, 2010
Figure 12-4. A/D Converter Sampling and A/D Conversion Timing
ADCS
Wait
period
Note
Conversion time Conversion time
Sampling
Sampling
timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
SAR
clear
SAR
clear
Transfer
to ADCR,
INTAD
generation
Successive conversion
Note For details of wait period, refer to CHAPTER 31 CAUTIONS FOR WAIT.
(2) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register. The higher 2 bits of the
conversion result are stored in FF09H and the lower 8 bits of the conversion result are stored in FF08H.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 12-5. Format of 10-Bit A/D Conversion Result Register (ADCR)
Symbol
Address: FF08H, FF09H After reset: 0000H R
FF09H FF08H
000000
ADCR
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration registers 0, 1 (ADPC0, ADPC1), the contents of ADCR
may become undefined. Read the conversion result following conversion completion before
writing to ADM0, ADS, ADPC0, and ADPC1. Using timing other than the above may cause an
incorrect conversion result to be read.
2. If data is read from ADCR, a wait cycle is generated. Do not read data from ADCR when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.