Datasheet

78K0/Kx2-L CHAPTER 12 A/D CONVERTER
R01UH0028EJ0400 Rev.4.00 407
Sep 27, 2010
Table 12-2. A/D Conversion Time Selection (1/3)
(1) 4.0 V ≤ AVREF ≤ 5.5 V
A/D Converter Mode Register 0
(ADM0)
Conversion Time Selection
FR2 FR1 FR0 LV1 LV0
Mode
fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz
Conversion
Clock (fAD)
0 0 0 264/fPRS 66.0 μ s 33.0 μ s 26.4 μ s fPRS/12
0 0 1 176/fPRS 44.0 μ s 22.0 μ s 17.6 μ s fPRS/8
0 1 0 132/fPRS 33.0 μ s 16.5 μ s 13.2 μ s fPRS/6
0 1 1 88/fPRS 22.0 μ s 11.0 μ s 8.8 μ s fPRS/4
1 0 0 66/fPRS 16.5 μ s 8.25 μ s 6.6 μ s fPRS/3
1 0 1 44/fPRS 11.0 μ s Setting prohibited fPRS/2
1 1 0 33/fPRS 8.25 μ s Setting prohibited fPRS/1.5
1 1 1
0 0 Standard
22/fPRS Setting prohibited fPRS
1 0 1 44/fPRS 11.0 μ s 5.5 μ s 4.4 μ s fPRS/2
1 1 1
1 1 High-speed 2
22/fPRS 5.5 μ s Setting prohibited fPRS
1 0 0 66/fPRS 16.5 μ s 8.25 μ s 6.6 μ s fPRS/3
1 1 0
1 0 High-speed 1
33/fPRS 8.25 μ s 4.125 μ s 3.3 μ s fPRS/1.5
Other than above Setting prohibited
Cautions 1. When rewriting FR2 to FR0, LV1, and LV0 to other than the same data, stop A/D conversion once
(ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time,
taking clock frequency errors into consideration.
Remark f
PRS: Peripheral hardware clock frequency