Datasheet

78K0/Kx2-L CHAPTER 12 A/D CONVERTER
R01UH0028EJ0400 Rev.4.00 406
Sep 27, 2010
Figure 12-3. Timing Chart When Comparator Is Used
ADCE
A/D voltage comparator
ADCS
LV0
(set to low-voltage mode or
high-speed mode)
Conversion
operation
Conversion
operation
Conversion
stopped
Conversion
waiting
Comparator operation
Note 1
Note 2
Notes 1. To stabilize the internal circuit, the time from setting ADCE to 1 to setting ADCS to 1 must be 1
μ
s or longer.
2. To stabilize the internal circuit, the time from setting LV0 to 1 (low-voltage mode or high-speed mode 2) to
setting ADCS to 1 must be 1
μ
s or longer (for operation mode setting, refer to Table 12-2).
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2, LV1, and LV0 to values other
than the identical data.
2. If data is written to ADM0, a wait cycle is generated. Do not write data to ADM0 when the
peripheral hardware clock (f
PRS) is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR
WAIT.