Datasheet
78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER
R01UH0028EJ0400 Rev.4.00 400
Sep 27, 2010
Remarks 1. fPRS: Peripheral hardware clock frequency
2. fSUB: Subsystem clock frequency
(2) Port mode register 4 (PM4)
This register sets port 4 input/output in 1-bit units.
When using the P42/PCL/SSI11/INTP6 pin for clock output, clear PM42 and the output latches of P42 to 0.
PM4 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PM4 to FFH.
Figure 11-3. Format of Port Mode Register 4 (PM4)
Address: FF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 1 1 1 1 1 PM42 PM41 PM40
PM4n P4n pin I/O mode selection (n = 0 to 2)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Remark The figure shown above presents the format of port mode register 4 of 48-pin products
(78K0/KC2-L).
11.4 Operations of Clock Output Controller
The clock pulse is output as the following procedure.
<1> Select the clock pulse output frequency with bits 0 to 3 (CCS0 to CCS3) of the clock output selection register
(CKS) (clock pulse output in disabled status).
<2> Set bit 4 (CLOE) of CKS to 1 to enable clock output.
Remark The clock output controller is designed not to output pulses with a small width during output enable/disable
switching of the clock output. As shown in Figure 11-4, be sure to start output from the low period of the
clock (marked with * in the figure). When stopping output, do so after the high-level period of the clock.
Figure 11-4. Remote Control Output Application Example
CLOE
Clock output
**