Datasheet

78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER
R01UH0028EJ0400 Rev.4.00 399
Sep 27, 2010
11.3 Registers Controlling Clock Output Controller
The following two registers are used to control the clock output controller.
• Clock output selection register (CKS)
• Port mode register 4 (PM4)
(1) Clock output selection register (CKS)
This register sets output enable/disable for clock output (PCL) and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CKS to 00H.
Figure 11-2. Format of Clock Output Selection Register (CKS) (48-pin products of 78K0/KC2-L)
Address: FF40H After reset: 00H R/W
Symbol 7 6 5 <4> 3 2 1 0
CKS 0 0 0 CLOE CCS3 CCS2 CCS1 CCS0
CLOE PCL output enable/disable specification
0 Clock division circuit operation stopped. PCL fixed to low level.
1 Clock division circuit operation enabled. PCL output enabled.
PCL output clock selection
Note 1
CCS3 CCS2 CCS1 CCS0
f
SUB =
32.768 kHz
fPRS =
4 MHz
fPRS =
10 MHz
0 0 0 0 fPRS
Note 2
4 MHz 10 MHz
0 0 0 1 fPRS/2 2 MHz 5 MHz
0 0 1 0 fPRS/2
2
1 MHz 2.5 MHz
0 0 1 1 fPRS/2
3
500 kHz 1.25 MHz
0 1 0 0 fPRS/2
4
250 kHz 625 kHz
0 1 0 1 fPRS/2
5
125 kHz 312.5 kHz
0 1 1 0 fPRS/2
6
62.5 kHz 156.25 kHz
0 1 1 1 fPRS/2
7
−
31.25 kHz 78.125 kHz
1 0 0 0 fSUB 32.768 kHz
−
Other than above Setting prohibited
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If internal high-speed oscillation clock frequency is set to 8 MHz (R4M8MSEL = 0) by option byte and the
peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fIH) (XSEL = 0) when
1.8 V ≤ V
DD < 2.7 V, setting CCS3 = CCS2 = CCS1 = CCS0 = 0 (output clock of PCL: fPRS) is prohibited.
Caution Set CCS3 to CCS0 while the clock output operation is stopped (CLOE = 0).