Datasheet

78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER
R01UH0028EJ0400 Rev.4.00 398
Sep 27, 2010
CHAPTER 11 CLOCK OUTPUT CONTROLLER
78K0/KY2-L
(
μ PD78F055x)
78K0/KA2-L
( μ PD78F056x)
78K0/KB2-L
( μ PD78F057x)
78K0/KC2-L
( μ PD78F058x)
Item
16 Pins 20, 25, 32 Pins 30 Pins 40, 44 Pins 48 Pins
Clock output
controller
− √
Remark √: Mounted, −: Not mounted
11.1 Functions of Clock Output Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs. The clock selected with the clock output selection register (CKS) is output.
Figure 11-1 shows the block diagram of clock output controller.
Figure 11-1. Block Diagram of Clock Output Controller
(48-pin products of 78K0/KC2-L)
CLOE
8
PCL/SSI11/INTP6/P42
Clock
controller
Prescaler
Internal bus
CCS3
Clock output select register (CKS)
CCS2 CCS1 CCS0
Output latch
(P42)
PM42
Selector
f PRS
f PRS to f PRS /2
7
f SUB
11.2 Configuration of Clock Output Controller
The clock output controller includes the following hardware.
Table 11-1. Configuration of Clock Output Controller
Item Configuration
Control registers
Clock output selection register (CKS)
Port mode register 4 (PM4)
Port register 4 (P4)