Datasheet

78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1
R01UH0028EJ0400 Rev.4.00 351
Sep 27, 2010
<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.
<6> To stop the count operation, set TMHEn = 0.
If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock
frequency is f
CNT, the PWM pulse output cycle and duty are as follows.
• PWM pulse output cycle = (N + 1)/f
CNT
• Duty = (M + 1)/(N + 1)
Cautions 1. The set value of the CMP1n register can be changed while the timer counter is operating.
However, this takes a duration of three operating clocks (signal selected by the CKSn2 to CKSn0
bits of the TMHMDn register) from when the value of the CMP1n register is changed until the
value is transferred to the register.
2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after the
timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the same
value to the CMP1n register).
3. Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are
within the following range.
00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH
Remarks 1. For the setting of the output pin, refer to 8.3 (4) Port mode register 0 (PM0), port mode register 1
(PM1), port mode register 3 (PM3).
2. For details on how to enable the INTTMHn signal interrupt, refer to CHAPTER 17 INTERRUPT
FUNCTIONS.
3. 78K0/KY2-L, 78K0/KA2-L: n = 1
78K0/KB2-L, 78K0/KC2-L: n = 0, 1