Datasheet

78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1
R01UH0028EJ0400 Rev.4.00 348
Sep 27, 2010
Figure 8-13. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation (Operation When 01H ≤ CMP0n ≤ FEH)
00H
Count clock
Count start
8-bit timer counter Hn
CMP0n
TMHEn
INTTMHn
TOHn
01H N
Clear
Interval time
Clear
N
00H 01H N 00H 01H 00H
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter Hn clear
<3><1>
<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than 1
clock after the operation is enabled.
<2> When the value of the 8-bit timer counter Hn matches the value of the CMP0n register, the value of the timer
counter is cleared, and the level of the TOHn output is inverted. In addition, the INTTMHn signal is output at the
rising edge of the count clock.
<3> If the TMHEn bit is cleared to 0 while timer H is operating, the INTTMHn signal and TOHn output are set to the
default level. If they are already at the default level before the TMHEn bit is cleared to 0, then that level is
maintained.
Remarks 1. 01H ≤ N ≤ FEH
2. 78K0/KY2-L, 78K0/KA2-L: n = 1
78K0/KB2-L, 78K0/KC2-L: n = 0, 1