Datasheet

78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1
R01UH0028EJ0400 Rev.4.00 340
Sep 27, 2010
Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)
(78K0/KB2-L, 78K0/KC2-L Only)
TMHE0
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE0
0
1
Timer operation enable
TMHMD0 CKS02 CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0
Address: FF69H After reset: 00H R/W
CKS02
0
0
0
0
1
1
CKS01
0
0
1
1
0
0
CKS00
0
1
0
1
0
1
Count clock selection
Note 1
Other than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD01
0
1
TMMD00
0
0
Timer operation mode
Low level
High level
TOLEV0
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN0
0
1
Timer output control
Other than above
<7>
6
5
4
3 2 <1>
<0>
f PRS
f PRS /2
f
PRS /2
2
f PRS /2
6
f PRS /2
10
TM50 output
Note 2
Setting prohibited
f
PRS = 2 MHz
2 MHz
1 MHz
500 kHz
31.25 kHz
1.95 kHz
f
PRS = 5 MHz
5 MHz
2.5 MHz
1.25 MHz
78.13 kHz
4.88 kHz
f PRS = 10 MHz
10 MHz
5 MHz
2.5 MHz
156.25 kHz
9.77 kHz
Note 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz