Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 332
Sep 27, 2010
Figure 7-18. PWM Output Operation Timing
(a) Basic operation (active level = H)
Count clock
TM5n
CR5n
TCE5n
INTTM5n
TO5n
00H 01H FFH 00H 01H 02H N N + 1 FFH 00H 01H 02H M 00H
N
<2> Active level
<1> Inactive level
<3> Inactive level
<5> Inactive level
t
<2> Active level
(b) CR5n = 00H
Count clock
TM5n
CR5n
TCE5n
INTTM5n
01H00H FFH 00H 01H 02H
00H
FFH 00H 01H 02H M 00H
TO5n
L (Inactive level)
t
(c) CR5n = FFH
TM5n
CR5n
TCE5n
INTTM5n
TO5n
01H00H FFH 00H 01H 02H
FFH
<1> Inactive level
<2> Active level
FFH 00H 01H 02H
M 00H
<3> Inactive level
<2> Active level
<5> Inactive level
t
Remarks 1. <1> to <3> and <5> in Figure 7-18 (a) and (c) correspond to <1> to <3> and <5> in PWM output operation
in 7.4.4 (1) PWM output basic operation.
2. 78K0/KB2-L, 78K0/KC2-L: n = 0, 1