Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 331
Sep 27, 2010
(1) PWM output basic operation
Setting
<1> Set each register.
• Clear the port output latch (P17 or P33)
Note
and port mode register (PM17 or PM33)
Note
to 0.
• TCL5n: Select the count clock.
• CR5n: Compare value
• TMC5n: Stop the count operation, select PWM mode.
The timer output F/F is not changed.
TMC5n1 Active Level Selection
0 Active-high
1 Active-low
Timer output enabled
(TMC5n = 01000001B or 01000011B)
<2> The count operation starts when TCE5n = 1.
Clear TCE5n to 0 to stop the count operation.
Note 8-bit timer/event counter 50: P17, PM17
8-bit timer/event counter 51: P33, PM33
PWM output operation
<1> PWM output (TO5n output) outputs an inactive level until an overflow occurs.
<2> When an overflow occurs, the active level is output. The active level is output until CR5n matches the count
value of 8-bit timer counter 5n (TM5n).
<3> After the CR5n matches the count value, the inactive level is output until an overflow occurs again.
<4> Operations <2> and <3> are repeated until the count operation stops.
<5> When the count operation is stopped with TCE5n = 0, PWM output becomes inactive.
For details of timing, refer to Figures 7-18 and 7-19.
The cycle, active-level width, and duty are as follows.
• Cycle = 2
8
t
• Active-level width = Nt
• Duty = N/2
8
(N = 00H to FFH)
Remark 78K0/KB2-L, 78K0/KC2-L: n = 0, 1