Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 328
Sep 27, 2010
7.4.2 Operation as external event counter
The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter
5n (TM5n).
TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the
rising or falling edge can be selected.
When the TM5n count value matches the value of 8-bit timer compare register 5n (CR5n), TM5n is cleared to 0 and an
interrupt request signal (INTTM5n) is generated.
Whenever the TM5n value matches the value of CR5n, INTTM5n is generated.
Setting
<1> Set each register.
• Set the port mode register (PM17, PM30, or PM33)
Note
to 1.
• TCL5n: Select TI5n pin input edge.
TI5n pin falling edge → TCL5n = 00H
TI5n pin rising edge → TCL5n = 01H
• CR5n: Compare value
• TMC5n: Stop the count operation, select the mode in which clear & start occurs on match of TM5n and
CR5n, disable the timer F/F inversion operation, disable timer output.
(TMC5n = 00000000B)
<2> When TCE5n = 1 is set, the number of pulses input from the TI5n pin is counted.
<3> When the values of TM5n and CR5n match, INTTM5n is generated (TM5n is cleared to 00H).
<4> After these settings, INTTM5n is generated each time the values of TM5n and CR5n match.
Note 8-bit timer/event counter 50: PM17
8-bit timer/event counter 51: PM30 (78K0/KY2-L, 78K0/KA2-L (20-pin products))
PM34 or PM00 (78K0/KA2-L (25-pin products))
PM33 (78K0/KB2-L, 78K0/KC2-L)
Remark For how to enable the INTTM5n signal interrupt, refer to CHAPTER 17 INTERRUPT FUNCTIONS.
Figure 7-16. External Event Counter Operation Timing (with Rising Edge Specified)
TI5n
TM5n count value
CR5n
INTTM5n
00H 01H 02H 03H 04H 05H N − 1 N 00H 01H 02H 03H
N
Count start
Remarks 1. N = 00H to FFH
2. 78K0/KY2-L, 78K0/KA2-L: n = 1
78K0/KB2-L, 78K0/KC2-L: n = 0, 1
<R>