Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 323
Sep 27, 2010
Figure 7-10. Format of 8-Bit Timer Mode Control Register 51 (TMC51) (2/2)
(b) 78K0/KB2-L, 78K0/KC2-L
Address: FF43H After reset: 00H R/W
Note
Symbol <7> 6 5 4 <3> <2> 1 <0>
TMC51 TCE51 TMC516 0 0 LVS51 LVR51 TMC511 TOE51
TCE51 TM51 count operation control
0 After clearing to 0, count operation disabled (counter stopped)
1 Count operation start
TMC516 TM51 operating mode selection
0 Mode in which clear & start occurs on a match between TM51 and CR51
1 PWM (free-running) mode
LVS51 LVR51 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F clear (0) (default value of TO51 output: low)
1 0 Timer output F/F set (1) (default value of TO51 output: high)
1 1 Setting prohibited
In other modes (TMC516 = 0) In PWM mode (TMC516 = 1) TMC511
Timer F/F control Active level selection
0 Inversion operation disabled Active-high
1 Inversion operation enabled Active-low
TOE51 Timer output control
0 Output disabled (TO51 output is low level)
1 Output enabled
Note Bits 2 and 3 are write-only.
Cautions 1. The settings of LVS51 and LVR51 are valid in other than PWM mode.
2. Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC511, TMC516: Operation mode setting
<2> Set TOE51 to enable output: Timer output enable
<3> Set LVS51, LVR51 (refer to Caution 1): Timer F/F setting
<4> Set TCE51
3. When TCE51 = 1, setting the other bits of TMC51 is prohibited.
4. The actual TO51/TI51/P33/INTP4 pin output is determined depending on PM33 and P33 besides
TO51 output.
Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE51 to 0.
2. If LVS51 and LVR51 are read, the value is 0.
3. The values of the TMC516, LVS51, LVR51, TMC511, and TOE51 bits are reflected at the TO51 output
regardless of the value of TCE51.