Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 321
Sep 27, 2010
Figure 7-9. Format of 8-Bit Timer Mode Control Register 50 (TMC50) (78K0/KB2-L, 78K0/KC2-L Only)
Address: FF6BH After reset: 00H R/W
Note
Symbol <7> 6 5 4 <3> <2> 1 <0>
TMC50 TCE50 TMC506 0 0 LVS50 LVR50 TMC501 TOE50
TCE50 TM50 count operation control
0 After clearing to 0, count operation disabled (counter stopped)
1 Count operation start
TMC506 TM50 operating mode selection
0 Mode in which clear & start occurs on a match between TM50 and CR50
1 PWM (free-running) mode
LVS50 LVR50 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F clear (0) (default value of TO50 output: low level)
1 0 Timer output F/F set (1) (default value of TO50 output: high level)
1 1 Setting prohibited
In other modes (TMC506 = 0) In PWM mode (TMC506 = 1) TMC501
Timer F/F control Active level selection
0 Inversion operation disabled Active-high
1 Inversion operation enabled Active-low
TOE50 Timer output control
0 Output disabled (TO50 output is low level)
1 Output enabled
Note Bits 2 and 3 are write-only.
Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode.
2. Perform <1> to <4> below in the following order, not at the same time.
<1> Set TMC501, TMC506: Operation mode setting
<2> Set TOE50 to enable output: Timer output enable
<3> Set LVS50, LVR50 (refer to Caution 1): Timer F/F setting
<4> Set TCE50
3. When TCE50 = 1, setting the other bits of TMC50 is prohibited.
4. The actual TO50/TI50/P17 pin output is determined depending on PM17 and P17 besides TO50
output.
Remarks 1. In PWM mode, PWM output is made inactive by clearing TCE50 to 0.
2. If LVS50 and LVR50 are read, the value is 0.
3. The values of the TMC506, LVS50, LVR50, TMC501, and TOE50 bits are reflected at the TO50 output
regardless of the value of TCE50.