Datasheet

78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 319
Sep 27, 2010
Figure 7-8. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL51 0 0 0 0 0 TCL512 TCL511 TCL510
Count clock selection
Note 1
TCL512 TCL511 TCL510
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
0 0 0 TI51 pin falling edge
Note 2
0 0 1 TI51 pin rising edge
Note 2
0 1 0 fPRS 2 MHz 5 MHz 10 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
1 1 0 fPRS/2
8
7.81 kHz 19.53 kHz 39.06 kHz
1 1 1 TMH1 output
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
V
DD = 2.7 to 5.5 V: fPRS 10 MHz
VDD = 1.8 to 2.7 V: fPRS 5 MHz
2. Do not start timer operation with the external clock from the TI51 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to “0”.
Remark f
PRS: Peripheral hardware clock frequency