Datasheet
78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
R01UH0028EJ0400 Rev.4.00 318
Sep 27, 2010
7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
The following five registers are used to control 8-bit timer/event counters 50 and 51.
• Timer clock selection register 5n (TCL5n)
• 8-bit timer mode control register 5n (TMC5n)
• Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin products) only)
• Port mode register 0 (PM0), port mode register 1 (PM1), or port mode register 3 (PM3)
• Port register 0 (P0), port register 1 (P1), or port register 3 (P3)
(1) Timer clock selection register 5n (TCL5n)
This register sets the count clock of 8-bit timer/event counter 5n and the valid edge of the TI5n pin input.
TCL5n can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears TCL5n to 00H.
Remark 78K0/KY2-L, 78K0/KA2-L: n = 1
78K0/KB2-L, 78K0/KC2-L: n = 0, 1
Figure 7-7. Format of Timer Clock Selection Register 50 (TCL50) (78K0/KB2-L, 78K0/KC2-L Only)
Address: FF6AH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL50 0 0 0 0 0 TCL502 TCL501 TCL500
Count clock selection
Note 1
TCL502 TCL501 TCL500
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
0 0 0 TI50 pin falling edge
Note 2
0 0 1 TI50 pin rising edge
Note 2
0 1 0 fPRS 2 MHz 5 MHz 10 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
1 0 0 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
1 1 0 fPRS/2
8
7.81 kHz 19.53 kHz 39.06 kHz
1 1 1 fPRS/2
13
0.24 kHz 0.61 kHz 1.22 kHz
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the fPRS
operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. Do not start timer operation with the external clock from the TI50 pin when the internal high-speed
oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem
clock, or when in the STOP mode.
Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to “0”.
Remark f
PRS: Peripheral hardware clock frequency
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