Datasheet

78K0/Kx2-L CHAPTER 1 OUTLINE
R01UH0028EJ0400 Rev.4.00 19
Sep 27, 2010
1.4.2 78K0/KA2-L
(1) 20-pin products
PORT 0
PORT 2
PORT 3
POWER ON CLEAR/
LOW VOLTAGE
INDICATOR
POC/LVI
CONTROL
RESET CONTROL
PORT 6
P60, P61
2
P121, P122, P125
3
PORT 12
SYSTEM
CONTROL
RESET/P125
X1/P121
X2/EXCLK/P122
INTERRUPT
CONTROL
A/D CONVERTER
AVREF
INTP0/P00
SERIAL
INTERFACE IICA
SDAA0/P61
SCLA0/P60
INTERNAL
HIGH-SPEED
RAM
78K/0
CPU
CORE
FLASH
MEMORY
8-bit TIMER H1
8-bit TIMER 51
WATCHDOG TIMER
16-bit TIMER/
EVENT COUNTER 00
TI000/P00
SERIAL
INTERFACE UART6
LINSEL
ON-CHIP DEBUG
INTERNAL
HIGH-SPEED
OSCILLATOR
INTERNAL
LOW-SPEED
OSCILLATOR
OPERATIONAL
AMPLIFIER 0
Note
AMP0+
Note
/P22
AMP0-
Note
/P20
AMP0OUT
Note
/PGAIN
Note
/P21
TO00/TI010/P01
3
P00, P01
P20 to P25
6
P30 to P32
6
INTP1/P30, INTP2/P31, INTP3/P32
TOH1/P30
RxD6/P61<LINSEL>
RxD6/P61<LINSEL>
RxD6/P61
TI51/P30
TxD6/P60
2
3
ANI0/P20 to ANI5/P25
TOOLC0/X1, TOOLC1/P31
TOOLD0/X2, TOOLD1/P32
3
VOLTAGE
REGULATOR
REGC
VSSVDD
Note
μ PD78F0565, 78F0566, 78F0567 (products with operational amplifier) only
Cautions 1. V
SS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to
a stabilized GND (= 0 V).
2. Connect the REGC pin to V
SS via a capacitor (0.47 to 1 μ F).
3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI5/P25 are set
in the analog input mode after release of reset.
4. RESET/P125 immediately after release of reset is set in the external reset input.