Datasheet

78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
R01UH0028EJ0400 Rev.4.00 274
Sep 27, 2010
(4) Operation in clear & start mode entered by TI000 pin valid edge input
(CR000: capture register, CR010: capture register)
Figure 6-29. Block Diagram of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register)
Timer counter
(TM00)
Clear
Output
controller
Capture register
(CR000)
Capture
signal
Capture signal
Interrupt signal
(INTTM010)
Interrupt signal
(INTTM000)
Capture register
(CR010)
Operable bits
TMC003, TMC002
Count clock
Edge
detection
TI000 pin
Edge
detection
TI010 pin
Note
Selector
TO00
output
Note
TO00 pin
Note
Note The timer output (TO00) cannot be used when detecting the valid edge of the TI010 pin is used.
Figure 6-30. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Capture Register, CR010: Capture Register) (1/3)
(a) TOC00 = 13H, PRM00 = 30H, CRC00 = 05H, TMC00 = 0AH
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Capture & count clear input
(TI000 pin input)
Capture register
(CR000)
Capture interrupt
(INTTM000)
Capture register
(CR010)
Capture interrupt
(INTTM010)
TO00 output
10
R
S
T
O
L
M
N
P
Q
00
L
0000H
0000H
LM NOPQRST
This is an application example where the count value is captured to CR010, TM00 is cleared, and the TO00 output is
inverted when the rising or falling edge of the TI000 pin is detected.
When the edge of the TI010 pin is detected, an interrupt signal (INTTM000) is generated. Mask the INTTM000 signal
when it is not used.