Datasheet

78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

R01UH0028EJ0400 Rev.4.00 250

Sep 27, 2010

Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)

Address: FFBCH After reset: 00H R/W

Symbol 7 6 5 4 3 2 1 0

CRC00 0 0 0 0 0 CRC002 CRC001 CRC000

CRC002 CR010 operating mode selection

0 Operates as compare register

1 Operates as capture register

CRC001 CR000 capture trigger selection

0 Captures on valid edge of TI010 pin

1 Captures on valid edge of TI000 pin by reverse phase

Note

The valid edge of the TI010 and TI000 pin is set by PRM00.

If ES010 and ES000 are set to 11 (both edges) when CRC001 is 1, the valid edge of the TI000 pin cannot

be detected.

CRC000 CR000 operating mode selection

0 Operates as compare register

1 Operates as capture register

If TMC003 and TMC002 are set to 11 (clear & start mode entered upon a match between TM00 and

CR000), be sure to set CRC000 to 0.

Note When the valid edge is detected from the TI010 pin, the capture operation is not performed but the INTTM000

signal is generated as an external interrupt signal.

Caution To ensure that the capture operation is performed properly, the capture trigger requires a pulse two

cycles longer than the count clock selected by prescaler mode register 00 (PRM00).

Figure 6-7. Example of CR010 Capture Operation (When Rising Edge Is Specified)

Count clock

TM00

TI000

Rising edge detection

CR010

INTTM010

N − 3N − 2N − 1 N N + 1

Valid edge