Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 239
Sep 27, 2010
5.6.9 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-11. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
(78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L)
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1
(The CPU is operating on the high-speed system clock)
RSTOP = 1
X1 clock
External main system clock
MCS = 0
(The CPU is operating on the internal high-speed oscillation clock)
MSTOP = 1
Table 5-12. Conditions Before the Clock Oscillation Is Stopped and Flag Settings (78K0/KC2-L)
Clock
Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled)
Flag Settings of SFR
Register
Internal high-speed
oscillation clock
MCS = 1 or CLS = 1
(The CPU is operating on a clock other than the internal high-speed
oscillation clock)
RSTOP = 1
X1 clock
External main system clock
MCS = 0 or CLS = 1
(The CPU is operating on a clock other than the high-speed system clock)
MSTOP = 1
XT1 clock
External subsystem clock
CLS = 0
(The CPU is operating on a clock other than the subsystem clock)
OSCSELS = 0