Datasheet
78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 235
Sep 27, 2010
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (4/4)
(9) CPU clock changing from subsystem clock (D) to high-speed system clock (C)
Note
Note 78K0/KC2-L only
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL MSTOP
OSTC
Register
XSEL
Note
MCM0 CSS
(D) → (C) (X1 clock) 0 1 0
Must be
checked
1 1 0
(D) → (C) (external main system clock) 1 1 0
Must not be
checked
1 1 0
Unnecessary if these
registers are already
set
Unnecessary if the
CPU is operating with
the high-speed system
clock
Unnecessary if this
register is already set
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
(10) • HALT mode (E) set while CPU is operating with internal high-speed oscillation clock (B)
• HALT mode (F) set while CPU is operating with high-speed system clock (C)
• HALT mode (G) set while CPU is operating with subsystem clock (D)
Note
Status Transition Setting
(B) → (E)
(C) → (F)
(D) → (G)
Note
Executing HALT instruction
Note 78K0/KC2-L only
(11) • STOP mode (H) set while CPU is operating with internal high-speed oscillation clock (B)
• STOP mode (I) set while CPU is operating with high-speed system clock (C)
(Setting sequence)
Status Transition Setting
(B) → (H)
(C) → (I)
Stopping peripheral functions that
cannot operate in STOP mode
Executing STOP instruction
Note When transitioning to the STOP mode, it is possible to achieve low power consumption by setting RMC = 56H
first.
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figures 5-18 and 5-19.
2. EXCLK, OSCSEL: Bits 7 and 6 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS: Bit 4 of the processor clock control register (PCC)
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