Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 234
Sep 27, 2010
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (3/4)
(6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
RSTOP RSTS MCM0
(C) → (B) 0 Confirm this flag is 1. 0
Unnecessary if the CPU is operating
with the internal high-speed oscillation clock
(7) CPU clock changing from high-speed system clock (C) to subsystem clock (D)
Note
Note 78K0/KC2-L only
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
XTSTART EXCLKS OSCSELS
Waiting for
Oscillation
Stabilization
CSS
0 0 1 (C) → (D) (XT1 clock)
1
× ×
Necessary 1
(C) → (D) (external subsystem clock) 0 1 1 Unnecessary 1
Unnecessary if the CPU is operating
with the subsystem clock
(8) CPU clock changing from subsystem clock (D) to internal high-speed oscillation clock (B)
Note
Note 78K0/KC2-L only
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
RSTOP RSTS MCM0 CSS
(D) → (B) 0
Confirm this flag
is 1.
0 0
Unnecessary if the CPU is operating
with the internal high-speed
oscillation clock
↑
Unnecessary if
XSEL is 0
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figure 5-18 and 5-19.
2. MCM0: Bit 0 of the main clock mode register (MCM)
EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL)
RSTS, RSTOP: Bits 7 and 0 of the internal oscillation mode register (RCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×: Don’t care