Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 233
Sep 27, 2010
Table 5-6. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL MSTOP
OSTC
Register
XSEL
Note
MCM0
(B) → (C) (X1 clock) 0 1 0
Must be
checked
1 1
(B) → (C) (external main system clock) 1 1 0
Must not be
checked
1 1
Unnecessary if these
registers are already set
Unnecessary if the CPU
is operating with the
high-speed system
clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already
been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (refer to
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
Note
Note 78K0/KC2-L only
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
XTSTART EXCLKS OSCSELS
Waiting for
Oscillation
Stabilization
CSS
0 0 1 (B) → (D) (XT1 clock)
1
× ×
Necessary 1
(B) → (D) (external subsystem clock) 0 1 1 Unnecessary 1
Unnecessary if the CPU is operating
with the subsystem clock
Remarks 1. (A) to (I) in Table 5-6 correspond to (A) to (I) in Figures 5-18 and 5-19.
2. EXCLK, OSCSEL, EXCLKS, OSCSELS:
Bits 7 to 4 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
XTSTART, CSS: Bits 6 and 4 of the processor clock control register (PCC)
×: Don’t care