Datasheet
78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 231
Sep 27, 2010
Figure 5-19. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set
(Option Byte: LVISTART = 0), 78K0/KC2-L)
Power ON
Reset release
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
CPU: Operating
with internal high-
speed oscillation
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: Internal high-
speed oscillation
→ STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Operable
CPU: Internal high-
speed oscillation
→ HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operable
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Operable
CPU: Operating
with XT1 oscillation or
EXCLKS input
CPU: XT1
oscillation/EXCLKS
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input: Operating
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
(B)
(A)
(C)
(D)
(E)
(F)
(G)
(H)
(I)
VDD ≥ 1.61 V (TYP.)
V
DD ≥ 1.8 V (MIN.)
V
DD < 1.61 V (TYP.)
Note
Note
Note
Note
Note
Note When transitioning to the STOP mode, subsystem clock operation mode, and subsystem clock HALT mode, it
is possible to achieve low power consumption by setting RMC = 56H first.
Remark When LVI default start function enabled is set (option byte: LVISTART = 1), the CPU clock status changes to
(A) in the above figure when the supply voltage exceeds 1.91 V (TYP.), and to (B) after reset processing (12
to 51
μ
s).
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