Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 227
Sep 27, 2010
(3) Example of setting procedure when using the subsystem clock as the CPU clock
<1> Setting subsystem clock oscillation
Note
(Refer to 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of
setting procedure when using the external subsystem clock.)
Note The setting of <1> is not necessary when while the subsystem clock is operating.
<2> Switching the CPU clock (PCC register)
When CSS is set to 1, the subsystem clock is supplied to the CPU.
CSS PCC2 PCC1 PCC0 CPU Clock (fCPU) Selection
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
f
SUB 1
Other than above Setting prohibited
(4) Example of setting procedure when stopping the subsystem clock
<1> Confirming the CPU clock status (PCC and MCM registers)
Confirm with CLS and MCS that the CPU is operating on a clock other than the subsystem clock.
When CLS = 1, the subsystem clock is supplied to the CPU, so change the CPU clock to a clock other than
the subsystem clock.
CLS MCS CPU Clock Status
0 0 Internal high-speed oscillation clock
0 1 High-speed system clock
1
×
Subsystem clock
<2> Stopping the subsystem clock (OSCCTL register)
When OSCSELS is cleared to 0, XT1 oscillation is stopped (the input of the external clock is disabled).
Cautions 1. Be sure to confirm that CLS = 0 when clearing OSCSELS to 0. In addition, stop the watch
timer if it is operating on the subsystem clock.
2. The subsystem clock oscillation cannot be stopped using the STOP instruction.