Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 226
Sep 27, 2010
5.6.3 Example of controlling subsystem clock
The following two types of subsystem clocks
Note
are available.
• XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins.
• External subsystem clock: External clock is input to the EXCLKS pin.
When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as input port pins.
Note 78K0/KC2-L only
Cautions 1. The XT1/P123 and XT2/EXCLKS/P124 pins are in the input port mode after a reset release.
2. Do not start the peripheral hardware operation with the external clock from peripheral hardware
pins when the internal high-speed oscillation clock and high-speed system clock are stopped
while the CPU operates with the subsystem clock, or when in the STOP mode.
The following describes examples of setting procedures for the following cases.
(1) When oscillating XT1 clock
(2) When using external subsystem clock
(3) When using subsystem clock as CPU clock
(4) When stopping subsystem clock
(1) Example of setting procedure when oscillating the XT1 clock
<1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers)
When a value is specified for XTSTART and EXCLKS and OSCSELS are set to the values below, the system
switches from the port mode to the XT1 oscillation mode. set as any of the following, the mode is switched
from port mode to XT1 oscillation mode.
XTSTART EXCLKS OSCSELS
Operation Mode of
Subsystem Clock Pin
P123/XT1 Pin
P124/XT2/
EXCLKS Pin
0 0 1
1
× ×
XT1 oscillation mode Crystal/ceramic resonator connection
Remark ×: don’t care
<2> Waiting for the stabilization of the subsystem clock oscillation
Wait for the oscillation stabilization time of the subsystem clock by software, using a timer function.
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.
(2) Example of setting procedure when using the external subsystem clock
<1> Setting XT1 and XT2 pins, selecting XT1 clock/external clock and controlling oscillation (PCC and OSCCTL
registers)
When XTSTART is cleared to 0 and EXCLKS and OSCSELS are set to 1, the mode is switched from port
mode to external clock input mode. In this case, input the external clock to the EXCLKS/XT2/P124 pins.
XTSTART EXCLKS OSCSELS Operation Mode of
Subsystem Clock Pin
P123/XT1 Pin P124/XT2/
EXCLKS Pin
0 1 1 External clock input
mode
Input port External clock input
Caution Do not change the value of XTSTART, EXCLKS, and OSCSELS while the subsystem clock is
operating.