Datasheet
78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 218
Sep 27, 2010
Figure 5-16. Clock Generator Operation When Power Supply Voltage Is Turned On
(When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0))
0 V
1.61 V
(TYP.)
1.8 V
0.5 V/ms
(MIN.)
Internal high-speed
oscillation clock (f
IH)
CPU clock
High-speed
system clock (f
XH)
(when X1 oscillation
selected)
Subsystem clock (f
SUB)
(when XT1 oscillation
selected)
Note 3
Internal reset signal
Power supply
voltage (V
DD
)
Reset processing (12 to 51 μs)
<3>
Waiting for
voltage stabilization
(0.93 to 3.7 ms)
<1>
<2>
<4>
<4>
Internal high-speed oscillation clock
High-speed system clock
Switched by
software
Subsystem clock
Note 3
<5> <5>
X1 clock
oscillation stabilization time:
2
8
/fX to 2
18
/fX
Note 2
Starting X1 oscillation
is set by software.
Starting XT1 oscillation
is set by software.
Waiting for oscillation
accuracy stabilization
(102 to 407 μs)
Note 1
<1> When the power is turned on, an internal reset signal is generated by the power-on-clear (POC) circuit.
<2> When the power supply voltage exceeds 1.61 V (TYP.), the reset is released and the internal high-speed
oscillator automatically starts oscillation.
<3> When the power supply voltage rises with a slope of 0.5 V/ms (MIN.), the CPU starts operation on the internal
high-speed oscillation clock after the reset is released and after the stabilization times for the voltage of the
power supply and regulator have elapsed, and then reset processing is performed.
<4> Set the start of oscillation of the X1 or XT1 clock via software (refer to (1) in 5.6.1 Example of controlling high-
speed system clock and (1) in 5.6.3 Example of controlling subsystem clock).
<5> When switching the CPU clock to the X1 or XT1 clock, wait for the clock oscillation to stabilize, and then set
switching via software (refer to (3) in 5.6.1 Example of controlling high-speed system clock and (3) in 5.6.3
Example of controlling subsystem clock).
Notes 1. The internal voltage stabilization time includes the oscillation accuracy stabilization time of the internal
high-speed oscillation clock.
2. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal
high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC). If the CPU operates on the high-speed system clock (X1
oscillation), set the oscillation stabilization time when releasing STOP mode using the oscillation
stabilization time select register (OSTS).
3. 78K0/KC2-L only