Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 206
Sep 27, 2010
Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/fCPU
Main System Clock
High-Speed System
Clock
Note 1
Internal High-Speed Oscillation Clock
Note 1
Subsystem Clock
Note 2
CPU Clock (fCPU)
At 10 MHz Operation At 8 MHz (TYP.)
Operation
At 4 MHz (TYP.)
Operation
At 32.768 kHz Operation
fXP 0.2 μ s 0.25 μ s (TYP.) 0.5 μ s (TYP.)
−
fXP/2 0.4 μ s 0.5 μ s (TYP.) 1.0 μ s (TYP.)
−
fXP/2
2
0.8 μ s 1.0 μ s (TYP.) 2.0 μ s (TYP.)
−
fXP/2
3
1.6 μ s 2.0 μ s (TYP.) 4.0 μ s (TYP.)
−
fXP/2
4
3.2 μ s 4.0 μ s (TYP.) 8.0 μ s (TYP.)
−
fSUB/2
Note 2
− −
122.1 μ s
Notes 1. The main clock mode register (MCM) is used to set the main system clock supplied to CPU clock (high-
speed system clock/internal high-speed oscillation clock) (refer to Figures 5-5 and 5-6).
2. 78K0/KC2-L only
(3) Setting of operation mode for subsystem clock pin
The operation mode for the subsystem clock pin
Note
can be set by using bit 6 (XTSTART) of the processor clock
control register (PCC) and bits 5 and 4 (EXCLKS, OSCSELS) of the clock operation mode select register (OSCCTL)
in combination.
Note 78K0/KC2-L only
Table 5-3. Setting of Operation Mode for Subsystem Clock Pin (78K0/KC2-L)
PCC OSCCTL
Bit 6 Bit 5 Bit 4
XTSTART EXCLKS OSCSELS
Subsystem Clock Pin
Operation Mode
P123/XT1 Pin P124/XT2/EXCLKS
Pin
0 0 0 Input port mode Input port
0 0 1 XT1 oscillation mode Crystal resonator connection
0 1 0 Input port mode Input port
0 1 1 External clock input mode Input port External clock input
1
× ×
XT1 oscillation mode Crystal resonator connection
Caution Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is operating with
main system clock) when changing the current values of XTSTART, EXCLKS, and OSCSELS.
Remark ×: don’t care