Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 205
Sep 27, 2010
Figure 5-6. Format of Processor Clock Control Register (PCC)
(78K0/KC2-L)
Address: FFFBH After reset: 01H R/W
Note 1
Symbol 7 6 <5> <4> 3 2 1 0
PCC 0
XTSTART
Note 2
CLS CSS 0 PCC2 PCC1 PCC0
CLS CPU clock status
0 Main system clock
1 Subsystem clock
Notes 1. Bit 5 is read-only.
2. XTSTART is used in combination with EXCLKS and OSCSELS (bits 5 and 4 of the clock
operation mode select register (OSCCTL)). Refer to (3) Setting of operation mode for
subsystem clock pin.
Cautions 1. Be sure to clear bits 3 and 7 to “0”.
2. The peripheral hardware clock (f
PRS) is not divided when the division ratio of the PCC
is set.
Remark f
XP: Main system clock oscillation frequency
f
SUB: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/Kx2-L microcontrollers. Therefore,
the relationship between the CPU clock (f
CPU) and the minimum instruction execution time is as shown in Table 5-2.
CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/2
2
0 1 1 fXP/2
3
0
1 0 0 fXP/2
4
0 0 0
0 0 1
0 1 0
0 1 1
1
1 0 0
f
SUB/2
Other than above Setting prohibited