Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 204
Sep 27, 2010
Caution 3. The XT1 oscillator is a circuit with low amplification in order to achieve low-power
consumption. Note the following points when designing the circuit.
• Pins and circuit boards include parasitic capacitance. Therefore, perform
oscillation evaluation using a circuit board to be actually used and confirm that
there are no problems.
• Use the recommended resonator, which will be described in CHAPTER 28
ELECTRICAL SPECIFICATIONS after it is evaluated, when using the XT1
oscillator in the ultra-low power consumption oscillation (RSWOSC = 1).
• Make the wiring between the XT1 and XT2 pins and the resonators as short as
possible, and minimize the parasitic capacitance and wiring resistance. Note
this particularly when the ultra-low power consumption oscillation (RSWOSC = 1)
is selected.
• Configure the circuit of the circuit board, using material with little wiring
resistance.
• Place a ground pattern that has the same potential as V
SS as much as possible
near the XT1 oscillator.
• Be sure that the signal lines between the XT1 and XT2 pins, and the resonators
do not cross with the other signal lines. Do not route the wiring near a signal
line through which a high fluctuating current flows.
• The impedance between the XT1 and XT2 pins may drop and oscillation may be
disturbed due to moisture absorption of the circuit board in a high-humidity
environment or dew condensation on the board. When using the circuit board in
such an environment, take measures to damp-proof the circuit board, such as by
coating.
• When coating the circuit board, use material that does not cause capacitance or
leakage between the XT1 and XT2 pins.
(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 5-5. Format of Processor Clock Control Register (PCC) (78K0/KY2-L, 78K0/KA2-L, 78K0/KB2-L)
Address: FFFBH After reset: 01H R/W
Symbol 7 6 5 4 3 2 1 0
PCC 0 0 0 0 0 PCC2 PCC1 PCC0
Cautions 1. Be sure to clear bits 3 to 7 to 0.
2. The peripheral hardware clock (f
PRS) is not divided when the division ratio of the PCC is set.
Remark f
XP: Main system clock oscillation frequency
PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/2
2
0 1 1 fXP/2
3
1 0 0 fXP/2
4
Other than above Setting prohibited