Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 203
Sep 27, 2010
Figure 5-3. Format of Clock Operation Mode Select Register (OSCCTL)
(78K0/KY2-L, 78K0/KA2-L, 78K0/KB2-L)
Address: FF9FH After reset: 00H R/W
Symbol <7> <6> 5 4 3 2 1 0
OSCCTL EXCLK OSCSEL 0 0 0 0 0 0
EXCLK OSCSEL High-speed system clock
pin operation mode
P121/X1 pin P122/X2/EXCLK pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input
mode
Input port External clock input
Cautions 1. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of
the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
2. Be sure to clear bits 0 to 5 to 0.
Figure 5-4. Format of Clock Operation Mode Select Register (OSCCTL)
(78K0/KC2-L)
Address: FF9FH After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> <1> 0
OSCCTL EXCLK OSCSEL EXCLKS
Note
OSCSELS
Note
0 RSWOSC AMPHXT 0
EXCLK OSCSEL High-speed system clock
pin operation mode
P121/X1 pin P122/X2/EXCLK pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input
mode
Input port External clock input
RSWOSC AMPHXT XT1 oscillator oscillation mode selection
0 0 Low power consumption oscillation (default)
0 1 Normal oscillation
1
×
Ultra-low power consumption oscillation
Note EXCLKS and OSCSELS are used in combination with XTSTART (bit 6 of the processor clock
control register (PCC)). Refer to (3) Setting of operation mode for subsystem clock pin.
Cautions 1. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of
the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
2. Be sure to clear bits 0 and 3 to 0.