Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR
R01UH0028EJ0400 Rev.4.00 202
Sep 27, 2010
Remark fX: X1 clock oscillation frequency
fIH: Internal high-speed oscillation clock frequency
f
EXCLK: External main system clock frequency
f
XH: High-speed system clock frequency
fXP: Main system clock frequency
f
PRS: Peripheral hardware clock frequency
f
CPU: CPU clock frequency
fXT: XT1 clock oscillation frequency
f
EXCLKS: External subsystem clock frequency
f
SUB: Subsystem clock frequency
fIL: Internal low-speed oscillation clock frequency
5.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operation mode select register (OSCCTL)
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main OSC control register (MOC)
• Main clock mode register (MCM)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Peripheral enable register 0 (PER0)
(1) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system and subsystem clocks.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.