Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR R01UH0028EJ0400 Rev.4.00 201 Sep 27, 2010
Figure 5-2. Block Diagram of Clock Generator (78K0/KC2-L)
LSRSTOP RSTS RSTOP
OSCSELS EXCLKS RSWOSC AMPHXT
XT1/P123
XT2/EXCLKS
/P124
CPU
CSS PCC2CLS PCC1 PCC0
OSTS1 OSTS0OSTS2
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
MCM0 XSEL
MCS
MSTOP
STOP
EXCLK
OSCSEL
4
X1/P121
X2/EXCLK
/P122
XTSTART
XTSTART
fIL
fSUB
fXP
fXP
2
fSUB
2
f
XP
2
2
fXP
2
3
fXP
2
4
fXH
fX
f EXCLK
fXT
f EXCLKS
fIH
fCPU
fPRS
Processor clock
control register
(PCC)
Oscillation stabilization
time select register (OSTS)
Clock operation mode
select register
(OSCCTL)
Main clock
mode register
(MCM)
Main clock
mode register
(MCM)
Main OSC
control register
(MOC)
Internal bus
Internal bus
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
Crystal
oscillation
External input
clock
Subsystem
clock oscillator
Internal high-
speed oscillator
(4 MHz (TYP.)/
8 MHz (TYP.))
Internal low-
speed oscillator
(30 kHz (TYP.))
Peripheral
hardware
Watchdog timer,
8-bit timer H1
Prescaler
1/2
Main system
clock switch
Peripheral
hardware
clock switch
X1 oscillation
stabilization time counter
Oscillation
stabilization
time counter
status register
(OSTC)
Controller
To subsystem
clock oscillator
Selector
Option byte
1: Cannot be stopped
0: Can be stopped
Internal oscillation
mode register
(RCM)
Real-time counter,
clock output
Clock operation mode
select register
(OSCCTL)
Processor clock
control register
(PCC)
Select an oscillation
frequency by option byte