Datasheet

78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR R01UH0028EJ0400 Rev.4.00 200 Sep 27, 2010
Figure 5-1. Block Diagram of Clock Generator (78K0/KY2-L, 78K0/KA2-L, 78K0/KB2-L)
LSRSTOP RSTS RSTOP
CPU
PCC2 PCC1 PCC0
OSTS1 OSTS0OSTS2
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
MCM0 XSEL
MCS
MSTOP
STOP
EXCLK
OSCSEL
3
X1/P121
X2/EXCLK
/P122
f IL
f XP
f XP
2
f
XP
2
2
f XP
2
3
f XP
2
4
f IH
f XH
f X
fEXCLK
f PRS
f CPU
Clock operation mode
select register
(OSCCTL)
Select an oscillation
frequency by option byte
Main OSC
control register
(MOC)
Internal bus
Internal bus
Main clock
mode register
(MCM)
Processor clock
control register
(PCC)
Oscillation stabilization
time select register (OSTS)
Main clock
mode register
(MCM)
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
Internal high-
speed oscillator
(4 MHz (TYP.)/
8 MHz (TYP.))
X1 oscillation
stabilization time counter
Oscillation
stabilization
time counter
status register
(OSTC)
System
clock switch
Peripheral
hardware
clock switch
Controller
Prescaler
Selector
Internal low-
speed oscillator
(30 kHz (TYP.))
Peripheral
hardware
Watchdog timer,
8-bit timer H1
Option byte
1:
Cannot be stopped
0: Can be stopped
Internal oscillation
mode register
(RCM)