Datasheet

78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 196
Sep 27, 2010
Table 4-18. Settings of Port Mode Register and Output Latch When Using Alternate Function
(78K0/KC2-L) (3/3)
Alternate Function Pin Name
Function Name I/O
MUXSEL PM×× P××
SDAA0
Notes 1, 2
I/O
−
0 1
SI11 Input CSISEL = 0 1
×
P61
INTP10 Input
−
1
×
SO11 Output CSISEL = 0 0 0 P62
INTP9 Input
−
1
×
P63
Note 3
INTP8
Note 3
Input
−
1
×
P70 to P73,
P74
Note 4
,
P75
Note 4
KR0 to KR3, KR4
Note 4
, KR5
Note 4
Input
−
1
×
INTP0 Input
−
1
×
EXLVI Input
−
1
×
P120
(SO11)
Note 3
Output CSISEL = 1 0 0
X1
Note 5
− − × ×
P121
TOOLC0 Input
− × ×
X2
Note 5
− − × ×
EXCLK
Note 5
Input
− × ×
P122
TOOLD0 I/O
− × ×
P123 XT1
Note 5
− − × ×
XT2
Note 5
− − × ×
P124
EXCLKS
Note 5
Input
− × ×
P125 RESET
Note 6
Input
− × ×
Notes 1. During I
2
C communication, set SCLA0 and SDAA0 to N-ch open drain output (VDD tolerance) mode by using
POM6 register (refer to 4.3 (5) Port output mode register 6 (POM6)).
2. When using an input compliant with the SMBus specifications in I
2
C communication, select the SMBus input
buffer by using PIM6 register (refer to 4.3 (4) Port input mode register 6 (PIM6)).
3. 44-pin and 48-pin products only
4. 48-pin products only
5. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem
clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock
(EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using
OSCCTL register (for details, refer to 5.3 (1) Clock operation mode select register (OSCCTL) and (3)
Setting of operation mode for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121
to P124 pins are Input port pins).
6. Clear RSTM bit (bit 5 of RSTMASK register) to 0 when using P125 as an external reset input (RESET).
Remarks 1. ×: Don’t care
PM××: Port mode register
P××: Port output latch
2. Functions in parentheses ( ) can be assigned by setting MUXSEL register.
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