Datasheet

78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 193
Sep 27, 2010
Table 4-17. Settings of Port Mode Register and Output Latch When Using Alternate Function
(78K0/KB2-L) (2/2)
Alternate Function Pin Name
Function Name I/O
PM×× P××
P30 INTP1 Input 1
×
INTP2 Input 1
×
P31
TOOLC1 Input
× ×
INTP3 Input 1
×
P32
TOOLD1 I/O
× ×
INTP4 Input 1
×
TI51 Input 1
×
P33
TO51 Output 0 0
SCLA0
Notes 1, 2
I/O 0 1 P60
INTP11 Input 1
×
SDAA0
Notes 1, 2
I/O 0 1 P61
INTP10 Input 1
×
INTP0 Input 1
×
P120
EXLVI Input 1
×
X1
Note 3
− × ×
P121
TOOLC0 Input
× ×
X2
Note 3
− × ×
EXCLK
Note 3
Input
× ×
P122
TOOLD0 I/O
× ×
P125 RESET
Note 4
Input
× ×
Notes 1. During I
2
C communication, set SCLA0 and SDAA0 to N-ch open drain output (VDD tolerance) mode by using
POM6 register (refer to 4.3 (5) Port output mode register 6 (POM6)).
2. When using an input compliant with the SMBus specifications in I
2
C communication, select the SMBus input
buffer by using PIM6 register (refer to 4.3 (4) Port input mode register 6 (PIM6)).
3. When using the P121 and P122 pins to connect a resonator for the main system clock (X1, X2) or to input an
external clock for the main system clock (EXCLK), the X1 oscillation mode or external clock input mode must
be set by using OSCCTL register (for details, refer to 5.3 (1) Clock operation mode select register
(OSCCTL)). The reset value of OSCCTL is 00H (both P121 and P122 are input port pins).
4. Clear RSTM bit (bit 5 of RSTMASK register) to 0 when using P125 as an external reset input (RESET).
Remark ×: Don’t care
PM××: Port mode register
P××: Port output latch