Datasheet
78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 176
Sep 27, 2010
Figure 4-39. Format of Port Register (78K0/KC2-L)
7
0
Symbol
P0
6
0
5
0
4
0
3
0
2
P02
Note 1
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
R/W
P27
Note 2, 3
P2
P26
Note 2
P25
Note 2
P24
Note 2
P23
Note 2
P22
Note 2
P21
Note 2
P20
Note 2
FF02H 00H (output latch)
R/W
P17
P1
P16 P15 P14 P13 P12
Note 2
P11
Note 2
P10
Note 2
FF01H 00H (output latch)
0
P3
0 0 0 P33 P32 P31 P30
FF03H 00H (output latch) R/W
0
P4
Note 3
0 0 0 0 P42
Note 1
P41
Note 3
P40
Note 3
FF04H 00H (output latch) R/W
0
P6
0 0 0 P63
Note 3
P62 P61 P60
FF06H 00H (output latch) R/W
0
P7
0 P75
Note 1
P74
Note 1
P73 P72 P71 P70
FF07H 00H (output latch) R/W
0
P12
0 P125
P124
Note 4
P123
Note 4
P120 FF0CH 00H (output latch)
R/W
Note 5
P122
Note 4
P121
Note 4
m = 0 to 4, 6, 7, 12; n = 0 to 7
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. 48-pin products only
2. If this pin is set as an analog input and to input mode, do not access the output latch.
3. 44-pin and 48-pin products y
4. “0” is always read from the output latch of the pin in the X1 oscillation mode, XT1 oscillation mode, or
external clock input mode.
5. P121 to P125 are read-only.
<R>