Datasheet

78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 175
Sep 27, 2010
Figure 4-38. Format of Port Register (78K0/KB2-L)
7
0
Symbol
P0
6
0
5
0
4
0
3
0
2
0
1
P01
0
P00
Address
FF00H
After reset
00H (output latch)
R/W
R/W
R/W
0
P2
0 0 0 P23
Note 1
P22
Note 1
P21
Note 1
P20
Note 1
FF02H 00H (output latch)
R/W
P17
P1
P16 P15 P14 P13 P12
Note 1
P11
Note 1
P10
Note 1
FF01H 00H (output latch)
0
P3
0 0 0 P33 P32 P31 P30
FF03H 00H (output latch) R/W
0
P6
0 0 0 0 0 P61 P60
FF06H 00H (output latch) R/W
0
P12
0 P125 0 0 P120 FF0CH 00H (output latch) R/W
Note 3
P122
Note 2
P121
Note 2
m = 0 to 3, 6, 12; n = 0 to 7
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. If this pin is set as an analog input and to input mode, do not access the output latch.
2. “0” is always read from the output latch of the pin in the X1 oscillation mode or external clock input
mode.
3. P121, P122, and P125 are read-only.