Datasheet
78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 163
Sep 27, 2010
Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or
subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or
subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock
input mode must be set by using the clock operation mode select register (OSCCTL) (for details,
refer to 5.3 (1) Clock operation mode select register (OSCCTL) and (3) Setting of operation mode
for subsystem clock pin). The reset value of OSCCTL is 00H (all of the P121 to P124 pins are
Input port pins).
2. RESET/P125 is set in an external reset input after a reset release.
3. Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset
signal is generated during low level input, the reset status continues until the input rises to the
high level.
4. If using P120 to input the potential for an external low-voltage detector, connect P120 to the
measured voltage source through a resistor. Do not apply a voltage of V
DD or more to P120.
Figure 4-27. Block Diagram of P120 (1/2)
(1) 78K0/KB2-L
P120/INTP0/EXLVI
WR
PU
RD
WR
PORT
WRPM
PU120
Alternate
function
Output latch
(P120)
PM120
VDD
P-ch
PU12
PM12
P12
Selector
Internal bus
P12: Port register 12
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
<R>
<R>