Datasheet

78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 155
Sep 27, 2010
4.2.6 Port 6
78K0/KY2-L
(
μ PD78F055x)
78K0/KA2-L
( μ PD78F056x)
78K0/KB2-L
( μ PD78F057x)
78K0/KC2-L
( μ PD78F058x)
16 Pins 20, 25, 32 Pins 30 Pins 40 Pins 44, 48 Pins
P60/SCLA0/TxD6 P60/SCLA0/TxD6 P60/SCLA0/INTP11
P60/SCLA0/SCK11/
INTP11
P60/SCLA0/SCK11/
INTP11
P61/SDAA0/RxD6 P61/SDAA0/RxD6 P61/SDAA0/INTP10
P61/SDAA0/SI11/
INTP10
P61/SDAA0/SI11/
INTP10
− − −
P62/SO11/INTP9 P62/SO11/INTP9
− − − −
P63/INTP8
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6). When the P60 to P63 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 6 (PU6).
Input to the P60 and P61 pins can be specified through a normal input buffer or an SMBus input buffer in 1-bit units,
using port input mode register 6 (PIM6).
Output from the P60 to P63 pins can be specified as normal CMOS output or N-ch open-drain output (V
DD tolerance) in
1-bit units, using port output mode register 6 (POM6).
This port can also be used for serial interface data I/O, clock I/O, and external clock input.
Reset signal generation sets port 6 to input mode.
Cautions 1. To use P60/SCLA0/SCK11/INTP11 and P62/SO11/INTP9 of 78K0/KC2-L as general-purpose ports,
set serial operation mode register 11 (CSIM11) and serial clock selection register 11 (CSIC11) to
the default status (00H).
2. To use P60/SCLA0/TxD6 of 78K0/KY2-L and 78K0/KA2-L as general-purpose port, clear bit 0
(TXDLV6) of asynchronous serial interface control register 6 (ASICL6) to 0 (normal output of
TxD6).
Figures 4-22 to 4-25 show block diagrams of port 6.
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