Datasheet

78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS
R01UH0028EJ0400 Rev.4.00 126
Sep 27, 2010
4.2.1 Port 0
78K0/KY2-L
(
μ
PD78F057x)
78K0/KA2-L
(
μ
PD78F056x)
78K0/KB2-L
(
μ
PD78F057x)
78K0/KC2-L
(
μ
PD78F058x)
16 Pins 20 Pins 25 Pins 32 Pins 30 Pins 40 Pins 44 Pins 48 Pins
P00/TI000/
INTP0
P00/TI000/
INTP0
P00/TI000/
INTP0(/TOH1)
(/TI51)
P00/TI000 P00/TI000 P00/TI000 P00/TI000
P01/TO00/
TI010
P01/TO00/
TI010
P01/TO00/
TI010
P01/TO00/
TI010
P01/TO00/
TI010
P01/TO00
/TI010
P01/TO00/
TI010
P02/SSI11/
INTP5
P02/SSI11/
INTP5
P02/INTP7
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 to P02 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 0 (PU0).
This port can also be used for timer I/O, external interrupt request input, and chip select input of serial interface. The
timer I/O can be assigned to P00 of the 78K0/KA2-L (25-pin products) by setting the port alternate switch control register
(MUXSEL).
Reset signal generation sets port 0 to input mode.
Figures 4-1 to 4-3 show block diagrams of port 0.
Figure 4-1. Block Diagram of P00
P00/TI000/INTP0 (78K0/KY2-L, 78K0/KA2-L)
P00/TI000 (78K0/KB2-L, 78K0/KC2-L)
WR
PU
RD
WR
PORT
WR
PM
PU00
Alternate function
Output latch
(P00)
PM00
V
DD
P-ch
Selector
Internal bus
PU0
PM0
P0
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode register 0
RD: Read signal
WR××: Write signal
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