Datasheet

78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 105
Sep 27, 2010
Table 3-10. Special Function Register List: 78K0/KC2-L (6/6)
Bit No.
Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FFBAH TMC00 0 0 0 0 TMC003 TMC002 TMC001 <OVF00> R/W √ √
−
00H
248
FFBBH PRM00 ES110 ES100 ES010 ES000 0 0
PRM001 PRM000
R/W √ √
−
00H
253
FFBCH CRC00 0 0 0 0 0
CRC002 CRC001 CRC000
R/W √ √
−
00H
249
FFBDH TOC00 0
<OSPT00> <OSPE00> TOC004
<LVS00> <LVR00>
TOC001
<TOE00> R/W √ √
−
00H
251
FFBEH LVIM <LVION> 0 0 0 0
<LVISEL>
<LVIMD> <LVIF> R/W
√ √ −
00H
Note1
672
FFBFH LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0 R/W
√ √ −
00H
Note2
675
FFC0H to
FFDFH
− − − − − − − − − − − − − − −
FFE0H IF0L <SREIF6> <PIF5> <PIF4> <PIF3> <PIF2> <PIF1> <PIF0> <LVIIF> R/W
√ √
00H
598
FFE1H
IF0
IF0H
<TMIF010> <TMIF000> <TMIF50> <TMIFH0> <TMIFH1> <CSIIF10>
<STIF6> <SRIF6> R/W
√ √
√
00H
598
FFE2H IF1L
<PIF8>
Note4
<PIF7>
Note3
<RTCI
F>
<KRIF>
<TMIF
51>
<RTCII
F>
<PIF6>
Note3
<ADIF> R/W
√ √
00H
598
FFE3H
IF1
IF1H 0 0 0 <PIF11> <PIF10> <PIF9>
<CSIIF
11>
<IICAI
F0>
R/W
√ √
√
00H
598
FFE4H MK0L
<SREMK6> <PMK5> <PMK4> <PMK3> <PMK2> <PMK1> <PMK0> <LVIMK>
R/W
√ √
FFH
606
FFE5H
MK0
MK0H
<TMMK
010>
<TMMK
000>
<TMMK
50>
<TMMK
H0>
<TMMK
H1>
<CSIM
K10
<STMK
6>
<SRMK
6>
R/W
√ √
√
FFH
606
FFE6H MK1L
<PMK8>
Note4
<PMK7>
Note3
<RTCM
K>
<KRMK>
<TMMK
51>
<RTCI
MK>
<PMK6>
Note3
<ADMK>
R/W
√ √
FFH
606
FFE7H
MK1
MK1H 1 1 1
<PMK1
1>
<PMK1
0>
<PMK9
>
<CSIM
K11>
<IICAM
K0>
R/W
√ √
√
FFH
606
FFE8H PR0L
<SREPR6>
<PPR5> <PPR4> <PPR3> <PPR2> <PPR1> <PPR0> <LVIPR> R/W
√ √
FFH
613
FFE9H
PR0
PR0H
<TMPR
010>
<TMPR
000>
<TMP
R50>
<TMP
RH0>
<TMP
RH1>
<CSIPR
10>
<STPR
6>
<SRPR
6>
R/W
√ √
√
FFH
613
FFEAH PR1L
<PPR8>
Note4
<PPR7>
Note3
<RTCP
R>
<KRPR>
<TMPR
51>
<RTCIP
R>
<PPR6>
Note3
<ADPR>
R/W
√ √
FFH
613
FFEBH
PR1
PR1H 1 1 1
<PPR
11>
<PPR
10>
<PPR9>
<CSIP
R11>
<IICAP
R0>
R/W
√ √
√
FFH
613
FFECH to
FFEFH
− − − − − − − − − − − − − − −
FFF0H IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 R/W
− √ −
CFH
Note5
699
FFF1H to
FFFAH
− − − − − − − − − − − − − − −
FFFBH PCC 0
XTSTA
RT
<CLS> <CSS> 0 PCC2 PCC1 PCC0 R/W
√ √ −
01H 204
Notes 1. The reset values of LVIM vary depending on the reset source and setting of option byte.
2. The reset values of LVIS vary depending on the reset source.
3. 48-pin products only.
4. 44-pin and 48-pin products only.
5. Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value
corresponding to each product as indicated in Table 3-1 after release of reset.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
<R>