Datasheet
78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 101
Sep 27, 2010
Table 3-10. Special Function Register List: 78K0/KC2-L (2/6)
Bit No.
Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FF20H PM0 1 1 1 1 1
PM02
Note 1
PM01 PM00 R/W √ √
− FFH 167, 256
FF21H PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 R/W
√ √
−
FFH 167, 324,
345, 415,
440, 463,
573
FF22H PM2
PM27
Note2
PM26 PM25 PM24 PM23 PM22 PM21 PM20 R/W
√ √
−
FFH 167, 415,
440
FF23H PM3 1 1 1 1 PM33 PM32 PM31 PM30 R/W
√ √
−
FFH 167, 324,
345
FF24H PM4
Note2
1 1 1 1 1
PM42
Note 1
PM41
Note2
PM40
Note2
R/W √ √
− FFH
167, 385,
400, 573
FF25H PER0 RTCEN 0 0 0 0 0 0 0 R/W √ √ − 00H
212, 373
FF26H PM6 1 1 1 1
PM63
Note2
PM62 PM61 PM60 R/W √ √
− FFH
167, 463,
504, 573
FF27H PM7 1 1
PM75
Note 1
PM74
Note 1
PM73 PM72 PM71 PM70 R/W √ √
− FFH 167
FF28H ADM0
<ADCS>
0 FR2 FR1 FR0 LV1 LV0
<ADCE>
R/W √ √ − 00H 405
FF29H − − − − − − − − − − − − − − −
FF2AH POM6 0 0 0 0
POM63
Note2
POM62 POM61 POM60 R/W √ √
−
00H
180, 464,
504
FF2BH FPCTL 0 0 0 0 0 0 0
<FLMD
PUP>
R/W √ √
−
00H 713
FF2CH PM12 1 1 1 1 1 1 1 PM120 R/W √ √
−
FFH
167, 573,
676
FF2DH RSTMASK 0 0 RSTM 0 0 0 0 0 R/W √ √ − 00H 180
FF2EH ADPC0
ADPCS7 ADPCS6 ADPCS5 ADPCS4 ADPCS3 ADPCS2 ADPCS1 ADPCS0
R/W √ √
−
00H
FF2FH ADPC1 0 0 0 0 0
ADPCS10
ADPCS9 ADPCS8
R/W √ √
−
07H
181, 413,
437
FF30H PU0 0 0 0 0 0
PU02
Note 1
PU01 PU00 R/W √ √
−
00H 177
FF31H PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 R/W √ √ − 00H 177
FF32H − − − − − − − − − − − − − − −
FF33H PU3 0 0 0 0 PU33 PU32 PU31 PU30 R/W √ √ − 00H 177
FF34H
PU4
Note2
0 0 0 0 0
PU42
Note 1
PU41
Note2
PU40
Note2
R/W √ √
−
00H 177
FF35H − − − − − − − − − − − − − − −
FF36H PU6 0 0 0 0
PU63
Note2
PU62 PU61 PU60 R/W √ √
−
00H 177
FF37H PU7 0 0
PU75
Note 1
PU74
Note 1
PU73 PU72 PU71 PU70 R/W √ √
−
00H 177
FF38H to
FF3BH
− − − − − − − − − − − − − − −
FF3CH PU12 0 0 PU125 0 0 0 0 PU120 R/W √ √ − 20H 177
FF3DH RMC − − − − − − − − R/W − √ − 00H 691
FF3EH PIM6 0 0 0 0 0 0 PIM61 PIM60 R/W √ √ − 00H
179, 503
FF3FH
MUXSEL
Note2
0 0 0 0 0 CSISEL 0 0 R/W √ √ − 00H 183, 572
Notes 1. 48-pin products only.
2. 44-pin and 48-pin products only.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0, and
is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
<R>